1. Field of the Invention
This invention generally relates to digital-to-analog converters (DACs) and, more particularly, to a circuit using a CMOS switch driver that is particular useful for N metal-oxide-semiconductor (NMOS) current steering DACs.
2. Description of the Related Art
The dynamic performance of a high-speed current steering DAC is greatly influenced by the waveform of the differential control signals driving the current switch, generated using a switch driver circuit. Existing driver circuits can be divided in two main types: complementary MOS (CMOS) and current mode logic (CML).
FIG. 1 is a diagram of NMOS current steering cell using a CML switch driver (prior art). A CMOS circuit has a voltage swing from the negative power supply (i.e. 0V) to the positive power supply (Vdd0). It is compact in area and consumes current only when the data (or clock) is changing. In contrast, the CML switch driver is based on the logic family with the same name. The output signals V− and V+ are differential and have a reduced voltage swing between some voltage Vlow and the positive power supply (Vdd0). The circuitry consists of always-on current sources, differential current switches, and load resistors. The positive power supply voltage to the CML switch driver may be Vdd0, or Vdd1 (Vdd1>Vdd0), where Vdd1 is the positive potential for the current steering cell. The result is very fast operation at the cost of significant current consumption and a relatively large area. By choosing a proper resistor value and magnitude of current, the amplitude of the output signal and its rise and fall times can be optimized for driving the DAC current steering cell. For good performance, output signals (V+ and V−) should change as simultaneously as possible. The simultaneity of timing between the multiple current cells in a DAC is also critical. A minimum clock to Q delay (delay from rising clock edge to change in the output) is also important to minimize the effects of clock jitter and component mismatch on timing.
The values of V+ and V− enable current flow through either path of the DAC current steering cell. The value of the DAC current steering cell differential output current is responsive to the binary digital value of d. Although not shown, properly scaled equivalent circuitry would exist for each bit of the digital word, with the output of each current steering DAC cell being combined to supply an analog current equivalent to the digital word. Typically, this current is converted to a voltage outside the DAC cell using resistors, or a combination of resistors and other passive components such as transformers, baluns, inductors, or capacitors (not shown).
In the case of an NMOS DAC current steering cell, Vdd1, which is the highest potential, is typically the high voltage to which the cell is connected. The negative supply voltage of the NMOS type DAC current steering cell can be considered to be 0V and is same potential as the main substrate.
FIG. 2 is a diagram depicting an NMOS current steering DAC cell with a CMOS switch driver (prior art). CMOS type switch drivers have the advantages of CMOS circuits mentioned above. The driver can be implemented with thick oxide 10 devices allowing a large voltage swing at the cost of reduced rise and fall times and maximum switching speed. On the other hand, a CMOS driver implemented using thin oxide core devices is faster, but must operate with a lower voltage swing. The problem with the CMOS drivers is that the voltage levels (V+/V−) are not optimal for the DAC current steering cell. For a DAC with PMOS current sources and PMOS current switches, a core device CMOS switch driver is a reasonably good solution. A PMOS DAC current steering DAC can be operated efficiently with the V+/V− signal voltages between Vdd0 (Vdd0<Vdd1) and (0V).
But when NMOS current sources and switches are used, as is often desirable to take advantage of the inherently faster operation of the N-type devices, the voltage levels provided by a CMOS driver are not optimal. Alternatively stated, even if the high voltage supplied to the NMOS switch driver (D flip-flop) is less than Vdd1 (Vdd0<Vdd1), the V+/V− low voltage is still ground (0V). Thus, the voltage difference supplied to the DAC current steering cell (Vdd0 to (0V)) is larger than necessary to operate the NMOS current steering DAC cell efficiently. The high swing signals have two problems: the switch transistors must be thick oxide IO devices to be able to handle the large voltage, which is a severe speed penalty. Further, setting the low voltage level all the way to zero makes the transition longer and can cause unnecessary feedthrough to the output.
It would be advantageous if an NMOS DAC current steering still could be driven by a CMOS current switch driver supplying a low voltage switch signal greater than ground (0V).